More Info on AMD’s Bulldozer CPUs

Intel wasn’t the only major vendor that caught our attention at the ISSCC last week, as AMD gave a detailed overview of their “Bulldozer” architecture. The company emphasizes how at the core, the processors have “modules” and integrates two “tightly linked” slim processor cores. AMD also says that the cores integrate their own L1 caches, but share high-bandwidth resources like a floating point unit, L2 cache as well as fetch, decode and prediction units to allow “chip multi-threading (CMT)”. While Intel on the other hand uses “chip multi-processing”, which uses complete individual cores and multi-threading.

Specifications indicate that Bulldozer will run at 3.5 GHz and the chips are being built by GlobalFoundries in a 32nm process, and a single module that has two cores can house about 213 million transistors and covers only a 31mm surface area along with the L2 cache. The soon to be released 8-core processors will most likely have over a billion transistors because the chip will also integrate L3 cache with a HyperTransport 3.1 controller.


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